1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, it relates to an active matrix semiconductor device including a pixel part and a sensor part.
2. Description of the Background Art
A portable device has recently been increasingly loaded with a display or a sensor. FIG. 10 is a block diagram showing a panel part and an external IC part of a conventional display. Referring to FIG. 10, a pixel part 150, a data system driving circuit 151, a scanning system driving circuit 152 and level conversion circuits 101, 102, 103, 104 an 105 are formed on an identical panel 200 in the conventional display. Drain lines and gate lines are arranged on the pixel part 150 in the form of a matrix. The data system driving circuit 151 is provided for driving the drain lines. The scanning system driving circuit 152 is provided for driving the gate lines.
The level conversion circuits 101, 102, 103, 104 and 105 are employed for level-converting the amplitudes (3 to 5 V) of external signals HST, HCK, VCK, VST and RST to 8 to 15 V respectively. The signals RST, VST, VCK, HCK and HST received from an external IC 120 are principal signals included in a group of driving signals externally input in the panel 200, and FIG. 10 does not show all signals necessary for driving the pixel part 150. These signals are complementary signals, which are regularly present in pairs (e.g., RST and/RST). The external IC 120 stores a clock generator 121 including a crystal oscillator.
FIGS. 11 to 14 are timing charts of respective signals in the conventional display shown in FIG. 10. Operations of the conventional display are now described with reference to FIGS. 10 to 14.
First, clocks HCK1 and HCK2 and clocks VCK1 and VCK2 are regularly externally input in the panel 200 at certain timing. After a reset signal RST is out and goes high, the display starts writing data in the pixel part 150. The outline of this conventional driving sequence is now described.
(1) After the reset signal (RST) is out and goes high, the first gate line gate1 rises in synchronization with the signals VCK.
(2) Then, a pulse signal HST is generated in time with the clocks HCK. Thus, a drain line selection signal h-sw1 is activated. While the drain line selection signal h-sw1 is activated, a video signal is input in a drain line as shown in FIG. 14.
(3) When a final data line selection signal h-swn is activated, a signal hout is generated to indicate termination of data system scanning.
(4) Generation of the signal hout leads to the leading edge of a next gate line gate2 and generation of the signals HST.
(5) When the final gate line gateN rises upon repetition of the aforementioned operations (2) and (3), a signal vout indicating termination of single screen scanning is generated as shown in FIG. 12. FIG. 12 shows the relation between the signals VST, VCK1 and VCK2 and vout.
(6) The aforementioned signal vout leads to the leading edge of the gate line gate1 and generation of the signal HST again.
FIG. 13 shows the relation between a dot clock dotclk and the signals HCK or the signal HST. As shown in FIG. 13, six cycles of the dot clock dotclk correspond to one cycle of the signals HCK.
In the aforementioned driving system for the conventional display, the principal control signals RST, VST, VCK, HCK and HST for driving the data system driving circuit 151 and the scanning system driving circuit 152 are externally input in the panel 200 while these signals RST, VST, VCK, HCK and HST are formed by complementary signal pairs. Therefore, the number of signal lines wired to a connector part connecting the panel 200 with the external IC 120 is disadvantageously increased.
FIGS. 15 and 16 are schematic diagrams for illustrating a problem in a case of miniaturizing the panel 200. As shown in FIG. 15, a connector part 201 for external connection is connected to the panel 200. If the panel 200 including a pixel part is miniaturized in this state, the degree of size reduction of the connector part 201 cannot follow that of a miniaturized panel 200a as shown in FIG. 16. Therefore, the size of the connector part 201 problematically exceeds that of the panel 200a including a display part.